1. Field of the Invention
The present invention is related to a vertical non-volatile memory and a manufacturing method thereof. More particularly, the invention is related to a vertical non-volatile memory which can prevent dopant from diffusing and a method of manufacturing the same.
2. Description of Related Art
The non-volatile memory is a memory that can retain stored data after its power supply is shut down. Nowadays, the manufacturing method of the non-volatile read-only memory is mostly forming a trapping layer constituted of oxide-nitride-oxide (ONO) first. A memory adopting an ONO layer as the trapping layer is called a trapping layer memory. Afterwards, a poly-silicon gate is formed on the ONO layer, and finally a source region and a drain region are formed at the two sides of the ONO layer on a substrate.
However, as the size of components gets smaller, the trapping layer in the trapping layer memory also gets narrower. Consequently, charges stored in different bit positions are drawn closer such that the reliability is reduced. Accordingly, a vertical non-volatile memory is developed. A vertical non-volatile memory is constituted of several stacked semiconductor layers fabricated as a vertical source, a vertical drain and a vertical channel region. An ONO layer served as a trapping layer covers a top surface of the stacked semiconductor layers, and lastly word lines are used as a control gate. Thus, more non-volatile memories can be manufactured within a limited area.
However, since the source, the drain and the channel region are adjacent to one another in the vertical non-volatile memory, dopant diffusion tends to happen in junctions among the source, the drain and the channel region in a subsequent thermal treatment so as to change the sizes of the source, the drain and/or the channel region.